Centillium (Centillium Communications, Inc. ) : CopperFlite (TM) CT-L53SC08/CT-L73SC08

Octal-Port ADSL Transceiver ChipSet for Central Office

The CopperFlite™ CO CT-L53SC08 Octal-Port ADSL Transceiver Chipset for Central Office Applications consists of the CT-L53DC08 digital processor chip and the CT-L50AC08 analog front end (AFE) chip. It offers a complete suite of silicon and software features, from the analog interface to the consolidated bit sync, PCM and Utopia, for DSLAM, MDU, and DLC ADSL modem applications.

The chipset is configurable, on a per port basis, to support eight G.dmt, G.lite, or T1.413 Issue 2 ADSL modems. Ultra-low power consumption is achieved by use of Centillium as second generation DSP core and state-of-the-art mixed signal designs in the AFE. Programmability ensures long product lifetime without the need for costly hardware upgrades. Pin compatibility of the CopperFlite CO family with Centillium's CT-L21SC08 and CT-L50SC04 DSL chipset families eases migration of existing designs.

Features

• Common Silicon platform for all multi-mode ADSL
• Eight-port ADSL modem chipset for high density, low power CO and DLC applications
• Per port configurable for G.dmt or G.lite
• CopperFlite product family complies with
  • ITU-T G.992.1 (G.dmt) including Annex A, B, C, & H
  • ITU-T G.992.2 (G.lite) including Annex A & C
  • ANSI T1.413 Issue 2
• Ultra-low power consumption
• Supports flexible multi-protocol architectures
  • Utopia Level-2 for ATM applications up to 50 MHz
  • Two independent PCM buses (up to 16 MHz) for STM applications
  • Eight bit synchronous network interfaces
• Supports multi-service-oriented architectures
  • Dual or single latency mode
  • Dual-stream mode (VoPCM, Voice over PCM)
• Less than 1.5 square inches per port of PCB area (from Utopia to tip and ring)
• No external memory required, full Utopia interface (no glue logic needed), no costly VCXO required
• High performance (G.dmt or T1.413 Issue 2)
  • Up to 8.192 Mbps downstream
  • Up to 1024 Kbps upstream
  • Category 2 functionality: Trellis coding and Viterbi
  • Rate adaptive
• Serial or Parallel processor interfaces for OAM functions
• Pin compatible with CopperLite CT-L21SC08 and CopperFlite CT-L50SC04 solutions
• -40°C to +85°C operation

• Second-generation DSL specific DSP core plus dedicated hardware accelerators
• 0.18 micron CMOS with split power rail
  • 3.3 V compatible I/O interface
  • 1.8V supply for all internal logic
• Single, low-cost external crystal operation
• Field programmable for easy upgrades
• No external memory required
  • On-chip interleaver function
• Utopia Level-2, 50-MHz interface for ATM data transfers
  • Easily interfaced to SARs
  • Facilitates provisioning multiple virtual circuits and traffic classes
• Programmable Transmission Convergence layer supports
  • Full-rate framing modes 0, 1, 2, 3 and G.lite
  • Efficient framing mode for rate challenged links
  • Channelized data mode for operating low-delay PCM/voice channels simultaneously over the ADSL link
  • Bearer channel muxing/demuxing
  • Reed-Solomon FEC encode/decode
  • CRC scrambling/descrambling
  • Interleave/deinterleave
• ATM transmission convergence layer
  • Cell delineation, cell payload scrambling, idle cell insertion/deletion, performance statistics
• STM transmission convergence layer
  • Two PCM interfaces with HDLC frame buffering and rate matching function
• Compliant with G.994.1 (G.hs) and G.997.1 (G.ploam)
• Full start-up and fast retrain capability
• Supports embedded operations channel (EOC)
  • Allows implementation of rate adaptive links for different loop lengths and conditions
• Self and remote diagnostics
• Power management capabilities
• JTAG (IEEE 1149.1) boundary scan and memory BIST
• Parallel data interface (PDI) for operations and maintenance (OAM) functions at up to 50 MHz
• Serial peripheral interface (SPI) for 4-wire control of OAM functions
• Reference designs including documentation and technical applications support available

• Fully integrated AFE for ADSL
• Low-power, cost effective, mixed-signal CMOS device
• Glueless interface to the CT-L53DC08 digital processor chip
• n Single 3.3V power supply
• Differential analog I/O
  • Analog full scale input 1.5 Vpp
  • Analog full scale output 3.0 Vpp
• Low noise -153 dBm/Hz typical input referred
• Integrated programmable gain control for transmit and receive paths
• Integrated digital-to-analog and analog-to-digital converters for transmit and receive paths
• Integrated transmit and receive channel filtering for both full-rate and G.lite operation
• Reduces requirements on external circuits
  • Integrates all active circuits except transmit line driver
• Reference designs including documentation and technical applications support available

Information used to be available at:
http://www.centillium.com/products/co/l53sc08.html

Technology:	ADSL
Package:	unknown 0 Pin
Linux support:	No