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DSL Chip Database |
- Previous: ADSL Integrated Broadband Communications Processor
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- ADSL PHY subsystem based on TI C62x DSP, with integrated transceiver, codec, line driver and line receiver
- High performance MIPS 32-Bit RISC processor
- IEEE 802.3 PHY
- Two IEEE 802.3 MACs with Media Independent Interface (MII) and Quality of Service (QoS)
- USB 1.1 compliant transceiver
- Hardware accelerated ATM SAR
- Two VLYNQ™ interfaces for compatible high-speed expansion devices
- EJTAG, GIPO, UART, and FSER interfaces
- 324 BGA with 1.0-mm ball pitch
- Multiple reference designs for various applications
TI ( Texas Instruments Incorporated ) : AR7 |
AR7 Family of Single-Chip DSL Solutions
Features
| Technology: | ADSL |
| Package: | BGA 324 Pin |
| Linux support: | No |
web page used to be available at: www.ti.com
PDF documentation used to be available at: http://focus.ti.com/pdfs/bcg/ar7_fact_sheet.pdf If you are the producer of this chip and want to correct/update the presented information, please feel free to register for direct database access.
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Last update:
14.11. 2009
Last link check: 01.03. 2006 |
All registered names and trademarks are the property of their respective owners. No guarantee is given and no responsibility is taken for the information provided. © 2025 Thomas Martin Knoll knoll@chipweb.de Impressum Datenschutz |
Life Cycle Costing (LCC) |
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