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    ST (STMicroelectronics GmbH ) : TOSCA

    TOSCA CHIPSET : STLC60134 / STLC60135

    ST's TOSCA™ chip set is a two chip ADSL solution. It integrates the analog front end, Digital MultiTone (DMT) processor, interleaving RAM, and universal test and operations physical interface for ATM (UTOPIA) framer. It is also fully compatible with ANSI T1.413 Issue 2 standards.

    The STLC60135 is the DMT modem and ATM framer of the STMicroelectronics Tosca chipset. When coupled with STLC60134 analog front-end and an external controller running dedicated firmware, the product fulfils ANSI T1.413 Issue 2 DMT ADSL specification. The STLC60135 may be used at both ends of ADSL loop: ATU-C and ATU-R. The chip supports UTOPIA level 1 and UTOPIA level 2 interface and a non ATM synchronous bit-stream interface.

    • DTM modem for ADSL, compatible with the following standards:
      • ANSI T1.413 Issue 2
      • ITU-T G.992.1 (G.dmt)
      • ITU-T G.992.2 (G.lite)
    • Same chip for both ATU-C and ATU-R
    • Supports either ATM (Utopia level 1 & 2) or bitstream interface
    • 16 bit multiplexed microprocessor interface (little and big endian compatibility)
    • Analog Front End management
    • Dual latency paths: fast and interleaved
    • ATM's PHY layer: cell processing (cell delineation, cell insertion, HEC)
    • ADSL s overhead management
    • Reed Solomon encode/decode
    • Trellis encode/decode (Viterbi)
    • DMT mapping/ demapping over 256 carriers
    • Fine (2ppm) timing recover using Rotor and Adaptative Frequency Domain Equalizing
    • Time Domain Equalization
    • Front end digital filters
    • 0.35µm HCMOS6 Technology
    • 144 pin PQFP package
    • Power Consumption 1 Watt at 3.3V

    The Analog Front End ( STLC60134 ) is build in mixed digital and analog technology and embodies the analog functions of the TOSCA. Automatic gain control amplifiers, placed at the analog interface of transmit and receive paths, allow for line s high attenuation in order to keep acceptable noise level of the signal ADC s and DAC s resolution, that is 12-bit wide with 8.8MHz sampling rate. A built-in driver allows for single external clock generation using a XTAL (ATU-C) or a VCXO (ATU-R).

    • Rx automatic gain control: 0-31dB in 1dB steps
    • Two input ports allow selection of RX signals, e.g. with or without external attenuation
    • Second transmit port available (i.e. echo cancellation)
    • Programmable low pass and band pass filters
    • 12-bit DAC and ADC, sampling at 8.832MHz
    • Xtal: 35.328MHz, ±50ppm, the accuracy of the frequency is determined by the External XTAL
    • Direct connection to STLC60135DTM modem
    • Error correction on ADC output
    • Test interface for digital and analog sections
    • Analog and digital loop back modes

    Technology: ADSL
    Package: unknown 0 Pin
    Linux support: No

    external WWW: STMicroelectronics GmbH : http://us.st.com/stonline/bin/hilite.exe?file=/stonline/press/magazine/prodnews/2ndedi99/pnews1.htm&words=TOSCA http://us.st.com/stonline/bin/hilite.exe?file=/stonline/press/magazine/prodnews/2ndedi99/pnews1.htm&words=TOSCA

    external PDF: STMicroelectronics GmbH : http://us.st.com/stonline/books/pdf/docs/5878.pdf PDF documentation used to be available at: http://us.st.com/stonline/books/pdf/docs/5878.pdf
    If you are the producer of this chip and want to correct/update the presented information, please feel free to register for direct database access.
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