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  • Transwitch (TranSwitch Corporation ) : TXC 05551-SARA II

    ATM Segmentation and Reassembly Device

    SARA II is a single-chip solution that performs complete segmentation and reassembly (SAR) for implementing low-cost ATM adapter cards, legacy LAN to ATM hubs, and routers. The device provides a PCI-based host interface to segment and reassemble packets directly in the host memory. In the transmit direction, the SARA II generates cells that conform to the ATM Forum traffic management service classes, such as CBR, VBR and ABR. Flexible traffic scheduling mechanisms support ABR traffic with associated RM cell processing. On the receive side, the SARA II allows simultaneous reassembly of over 64,000 connections directly in the host memory. The host buffers may be arbitrary sized blocks placed on arbitrary byte boundaries. An integrated SONET/SDH STS-1/STS-3c/STM-1 framer and overhead termination supports complete framing, cell delineation and cell rate decoupling functions. The UTOPIA interface supports connection to other line rates or ATM layer devices.


    • Full duplex segmentation and reassembly of multiple VCs up to 155 Mbit/s in each direction

    • Integrated SONET/SDH 155.52 Mbit/s framer

    • Optional 8-bit UTOPIA interface

    • PCI bus master and slave interface supports efficient, low latency burst transfers

    • Complete SAR functions for AAL5, AAL3/4 and AAL0 (null) in host memory

    • Support for AAL1

    • Supports over 64,000 virtual connections on transmit and receive

    • Supports non-contiguous variable size packet buffers providing scatter and gather function with arbitrary byte alignment and byte order.

    • Flexible scheduler provides per-connection rate management for VBR and CBR

    • Programmable RISC core supports customization and vendor specific additional features

    • Supports ATM Forum ABR traffic flow control including automatic RM cell insertion and management

    • Reassembly on the basis of any arbitrary sub-field of the 24/28-bit VPI/VCI field

    • Supports host-controlled OAM/Signaling cell insertion and extraction

    • Supports ATM Forum MIB

    • Boundary scan capability (IEEE 1149.1)

    • Single +3.3V, +/-5% power supply

    Documentation used to be available under: AND

    Technology: unknown
    Package: BGA 225 Pin

    external WWW: TranSwitch Corporation : web page used to be available at:

    external PDF: TranSwitch Corporation : PDF documentation used to be available at:
    If you are the producer of this chip and want to correct/update the presented information, please feel free to register for direct database access.
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