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The functions of this SAR controller are most of the ATM layer,
segmentation and reassembly(SAR) and DMA/buffer management
functions. The ATM interfacechip set is a two-chip set, partitioned into
transmit and receivefunctions, This ATM interface chip set is designed to
provide network interface functionsat a similar level as those provided by a
The chip set can accommodate up to 65K VC's, and up to 8K buffers;external high-speed RAM (such as static RAM) holds stateinformation such as buffer descriptors and VCI's. There can bemultiple buffers queued for transmission on any given VC. Thetransmit side has a flexible transmit rate structure, with up to eightdifferent peak rates, and a leaky bucket-based metering schemewhich can have individual parameters for each VC. Other features of this part are
- On transmit, packet buffers are queued to the FRED,
which fragments the packets into standard cells and meters them into the network
over virtual circuits at peak and average rates specified a priori by software.
- On receive, cells are accepted from the line, with multiple frames possibly
interleaved together, and the cells are verified, headers are stripped, the user data is reassembled into frames, then enqueued for the receiver software when the entire frame has been received.
The TXC 05501/5601 chip set is function compatible to National Semiconductors FRED but can operate at higher speeds.
- up to 8000 packets segments/reassembles simultaneously
- Performs AAL3/5 processing as well as AAL5
- Manages constant bit rate (CBR) traffic
- Selectable packet CRC per connection
- B-ISDN header and CRC generation and Checking
- microprocessor and packet RAM interface
- operates at higher speed to provide true 155 Mb/s
|PQFP 208 Pin
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