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FRED chip set
The adaptive ATM FRED chips are designed to be used inequipment which interfaces to an ATM network. The functionsincluded are most of the ATM layer, segmentation and re assembly(SAR) and DMA/buffer management functions. The ATM interfacechip set is a two-chip set, partitioned into transmit and receivefunctions, which we refer to as "FRED"(Fragmentation-Re assembly Engine with DMA). This ATMinterface chip set is designed to provide network interface functionsat a similar level as those provided by a LAN controller:
The chip set can accommodate up to 65K VC's, and up to 8K buffers;external high-speed RAM (such as static RAM) holds stateinformation such as buffer descriptors and VCI's. There can bemultiple buffers queued for transmission on any given VC. Thetransmit side has a flexible transmit rate structure, with up to eightdifferent peak rates, and a leaky bucket-based metering schemewhich can have individual parameters for each VC. FRED supportsboth AAL3/4 and AAL5 concurrently, selectable on a VC-by-VCbasis. It also has an AAL bypass mechanism which allows access to"raw cells", again selectable VC-by-VC. The FRED chip set is function compatible to TranSwitchs TXC 05501/5601.
- On transmit, packet buffers are queued to the FRED, which fragments the packets into standard cells and meters them into the network over virtual circuits at peak and average rates specified a priori by software.
- On receive, cells are accepted from the line, with multiple frames possibly interleaved together, and the cells are verified, headers are stripped, the user data is reassembled into frames, then enqueued for the receiver software when the entire frame has been received.
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