|
|
|
Chips | |
|
NICs |
|
|
Links |
|
|
| |
| New Chip | |
| New NIC | |
|
| |
|
Register | |
|
Login | |
|
| |
|
About |
ATM Chip Database |
- Previous: µPD98410 1.2G ATM SWITCH LSI (NEASCOT-X10)
- Up: List all producers
- Next: µPD98412 Advanced 1.5G ATM SWITCH LSI (NEASCOT-X15)
- implements the 155.52 Mbps SONET STS-3c/SDH STM-1 framer format
- Conforms to ATM Forums UNI 3.1
- Conforms to ATM Forum UTOPIA Interface Level II Vers. 1.0
- Supports 16-bit and 8-bit multi-PHY interface (max. 800 Mbps)
- Supports multiplexed status polling mode and parity bit
- Provides 2-type management interface for control
- includes on-chip clock recovery
- Provides abundant OAM functions
- 3.3 V power supply (can connect directly 5 V TTL level)
NEC (NEC ) : µPD98411 |
µPD98411 (NEASCOT-P40)
The NEASCOT -P40 contains four times the functionality of the NEASCOT-P30. Features are
| Technology: | 0.35µ CMOS |
| Package: | PQFP 240 Pin |
http://www.ee.nec.de/applications/communication/z_products/assp/atm/upd98411.html
PDF documentation used to be available at: http://www.ee.nec.de/_pdf/S12953EJ4V0DS00.PDF If you are the producer of this chip and want to correct/update the presented information, please feel free to register for direct database access.
|
Last update:
14.11. 2009
Last link check: 01.03. 2006 |
All registered names and trademarks are the property of their respective owners. No guarantee is given and no responsibility is taken for the information provided. © 2024 Thomas Martin Knoll knoll@chipweb.de Impressum Datenschutz |
|