ATM ChipWeb logo



New Chip



ATM Chip Database

  • Up: List all producers

    Hitachi (Hitachi Semiconductor (America) Inc. ) : HD64556

    622 Mbit/s SAR controller

    Hitachi's 622-Mbit/s cell-processing solution is the NewPort architecture. This chipset is comprised of the HD64556 hardware accelerator and a Hitachi SH-3 RISC processor. The set does full-duplex 622 Mbits/s over ATM, hardware accelerating on the MPOA and LANE standards, and full hardware-based QoS function. It also handles CBR, VBR and ABR classes of service. The HD64556 chip doesn't integrate the MPOA protocol on-chip, but rather accelerates the MPOA and other standards. Hitachi plans to follow its 622-Mbit/s ATM announcement with a 155-Mbit/s solution having the same basic architecture.

    Although ATM is a cell-based protocol, the NewPort architecture handles both cells and packets. The latter can be either IP or frame-relay type. According to Hitachi, a number of designers have expressed interest in using it as a packet engine to handle IP packets at 622 line rates.

    Connection to the physical layer takes place over a standard ATM UTOPIA interface. By necessity, the 622-Mbit/s connections are through an optical fiber connection. The UTOPIA, however, allows connection to quad OC-3 155 ports. Alternatively, one could connect to four 155-Mbit/s connections over analog UTP Cat 5 twisted-pair wires. At the other end of the NewPort architecture is a 66-MHz PCI interface. This connects into the backplane of the customer's switch and its host CPU.

    Key to the NewPort architecture is a separate SH-3 RISC processor. The SH-3 handles tasks that aren't directly related to cell processing. This processor lies outside the packet or cell data flow. It sits off of a separate bus accelerator implemented in a glue chip (an EPLD). This glue chip separates the buses, allowing maximum memory bandwidth on the 64-bit local bus connected to the hardware accelerator, while the SH-3 performs batch-oriented processing and resource cell management. In ATM systems using the ABR class of service, the flow of cells can be adjusted when network congestion occurs. An RM (resource management) cell is sent from the source to the destination, and back up from the destination to the source, telling it to "slow down your flow."

    Technology: unknown
    Package: unknown 0 Pin

    If you are the producer of this chip and want to correct/update the presented information, please feel free to register for direct database access.
ChipWeb Home

Last update: 14.11. 2009
Last link check: 01.03. 2006
All registered names and trademarks are the property of their respective owners.
No guarantee is given and no responsibility is taken for the information provided.
© 2024     Thomas Martin Knoll   Impressum   Datenschutz
back Kirche Reichenbach Vogtland