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ATM Chip Database |
- Previous: MB 86681 Enhanced ATM Self Routing Switch Element
- Up: List all producers
- Next: MB 86684 ITC25
- Implements framed and cell based physical layer OAM (PL-OAM) functions or FI, F2 and F3 flows
- Supports F4/F5 OAM cell insertion /extraction
- Maintenance of statistics for all active per virtual circuits, including cell and error and OAM statistics
- On-chip DMA controller for high-speed transfer of statistics and inserted/extracted cells to/from system memory
- Interfaces directly to MB86689 Address Translation Controller to perform real-time cell header translation
- JTAG compliant
Fujitsu (Fujitsu Microelectronics Europe ) : MB 86683 |
Network Termination Controller NTC
The NTC is a full-duplex network terminator which is designed to implement Transmit Convergence (TC) sub-layer functions for physical media based on SDH/SONET, SDH, DS3 and E3. The device includes a generic 8-bit parallel interface to an external transceiver which is only required to provide serial/parallel conversion and the clock recovery function.
NTC Applications
The NTC is ideally suited to applications in ATM adapter cards and hubs. It can be used for UNI or NNI applications and conforms to the relevant specifications. Two possible configurations involving the NTC are shown. In the ATM terminal equipment, the NTC is connected to the Adaptation Layer Controller (ALC). It takes the ATM cells generated by the ALC and performs all the framing functions required by the selected physical media. An external transceiver handles media-dependent functions such as line coding, clock recovery etc. The NTC also scrambles the payload data using one of two polynominals. If no user cells are available, the NTC will generate idle cells to maintain a constant cell stream on the network. Other cell types such as signalling cells can be inserted into the cell flow using the on-chip DMA controller. In the receive direction, the NTC synchronizes to the framed data and to the ATM cells. Statistics information is extracted from the framing bytes and the payload data unscrambled. The statistics collected are stored on a per virtual-circuit basis, either on-chip or local memory. The NTC contains a cell buffer which effectively de-couples network and system clocks. Cells are temporarily stored here while optional address translation on the VPI/VCI fields of received cell headers is performed by the ATC. Alternatively, the ALC handles partial address translation based on the sub-set of VP and VC bits. The relevant header fields are passed across a local interface on a per-byte basis. Once the ATC has completed any translation the new header value is returned to the NTC, appended to the cell information field, and the cell output to the ALC across the asynchronous cell stream interface.The part is packaged in 176 pin PQFP.
| Technology: | unknown |
| Package: | PQFP 176 Pin |
If you are the producer of this chip and want to correct/update the presented information, please feel free to register for direct database access.
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Last update:
14.11. 2009
Last link check: 01.03. 2006 |
All registered names and trademarks are the property of their respective owners. No guarantee is given and no responsibility is taken for the information provided. © 2025 Thomas Martin Knoll knoll@chipweb.de Impressum Datenschutz |
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