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  • Philips (Philips Research Laboratories ) : CMC155


    This chip is no longer in production, unfortunately.

    Philips Research in Aachen, Germany has been implemented a core element of a 6x25Mb/s stackable switch. CMC155 is based on Asynchronous Transfer Mode (ATM) technology and features

    • full-duplex 155Mb/s ATM FORUM user network interface
    • two full-duplex 155Mb/s UTOPIA interfaces for networking
    • administration of 1024 virtual connections on a physical link (header translation)
    • bandwidth supervision for individual connections (policing)
    • storage of asynchronously arriving ATM user cells
    • prioritized switching of buffered cells to the various outputs
    • patented circuit for efficient management of the cell buffer
    These generic ATM layer functions integrated into one chip provide a unique architecture for a low-cost, scalable network. Each user may insert up to 155 Mb/s of data at the User Network Interface (UNI) of the CMC into the network. Recognizing certain entries in the header, the destination CMC155 will remove data cells from the network and route them to its UNI output. Increasing the throughput , the double-ring topology renders ultra-fast broadcast and selfhealing facilities. Before the ATM hardware mixes the user data with the traffic arriving on both network ports, certain traffic parameters associated with each virtual connection have to be negotiated with the switch control software in order to not exceed the maximum affordable throughput. An embedded CPU per CMC155 element provides linearly growing CPU power for typical ATM software tasks such as signaling & call admission control, network & resource management, operation & maintenance.While the chip architecture allows immediate integration of an on-chip CPU, the initial version of the chip needs an external CPU. The ATM processor CMC155 has been designed in a 0.5 micron technology and measures 144 sqmm. It is available in samples with a 208-pin quad flat package and has a power dissipation of less than 1W.

    Physical layer interface

    • 155Mb/s User Network Interface port
    • ATM FORUM UNI 4.0 compatible
    • UTOPIA Level-1 octett handshake interface
    • 8-bit parallel data
    • optional Parity lines
    • optional Header Error Check
    • 2x bidirectional 155 Mb/s switching ports
    • UTOPIA Level-1 octett handshake interface
    • enhanced clock circuitry: direct coupling of CMC155 on printed circuit board
    • standard optical/electrical PHY devices are used for network interconnection

    ATM layer functions

    • VP/VC translator
    • - 2-stage translation for (a) standard user channels and (b) extra control/signalling channels (a) user transl. based on 1024 entries table, programmable insertion and extraction mask (b) extra translation based on 5 sets of freely programmable header processing registers for arbitrary matching and insertion of individual header bits Policing
    • full bandwidth range is subdivided into separate policing classes
    • usage parameter control for CLP=0+1 traffic: peak cell rate and cell delay variation. internal non-blocking 4x4 switch
    • on-chip shared Central Cell Memory for 128 cells
    • switching at network ports does not require extra routing tag, because switching control information is contained in ATM cell header at programmable locations
    • 4-class prioritized switching for various traffic categories
    • point-to-multipoint routing
    • separate output translator

    Traffic management

    • Flow Control/ Congestion Control
    • hardware supported Partial Packet Discard (simplified algorithm for distributed switching)
    • explicit forward congestion indication EFCI
    • hardware support for ABR flow control : RM cell filtering, on-chip RM cell queue
    • patented queue management for small cell buffers

    Control & Management functions

    • OAM cell filtering for F4/F5 segment flow
    • on-chip 32-cells OAM cell queue
    • fast read/modify/write for individual OAM payload words
    • HW support for fast network self healing and re-routing
    • Counters prescribed by standard Management Information bases
    • 32-bit counter for received/transmitted/discarded cells
    • 32-bit counter for cells with HEC violation or unknown VPCI
    • queue status for Central Cell Memory, RM queue and OAM queue

    Segmentation and Reassembly

    • AAL5
    • hardware CRC32 checker of AAL messages
    • hardware CRC32 generator
    • End-Of-message detection
    • hardware CRC10 checksum evaluation for individual cells
    • hardware CRC10 checksum generator
    • support functions for software Segmentation & Reassembly (SAR)
    • programmable periodic timer for isochronous segmentation

    CPU Interface

    • PCMCIA 2.01
    • asynchronous 16-bit multiplexed data/address bus
    • I/O read/write timing with WAIT signal handshake
    • 32bit DMA-write access to external DRAM
    • six interrupt lines to external CPU

    Chip characteristics

    • 200K gates complexity
    • 185 Kbit on-chip RAM (translation, cell memory, RM/OAM queue)
    • 3.3V supply voltage
    • 1 W power dissipation

    Technology: unknown
    Package: PQFP 208 Pin

    If you are the producer of this chip and want to correct/update the presented information, please feel free to register for direct database access.
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