The ATMizer II Application-Specific Standard Product is ahighly integrated ATM segmentation and reassembly (SAR) engine optimized forinter-networking and native ATM applications. The L64363 supports full duplexTx/Rx operation at 155 Mbps (OC-3), and is the second generation device withinLSI Logic's ATMizer product family.
A primary feature of the ATMizer product family is the flexibility offered by the ATM Processing Unit (APU), which is based on an embedded MiniRISC CPU Core. The APU allows users to modify operation of the device, accommodate changes in ATM specifica-tions, and differentiate their products through software. The L64363 integrates the APU with other key functional blocks to offer networking equipment designers both a flexible and high-performance solution for their system needs.Features include
The EDMA hardwired SAR functionality is optimized for AAL5 traffic, and assists the APU in segmentation and reassembly, and memory management tasks (support for AAL0, 1, 3/4, is also supported through APU assist).
Connections with different Quality of Service (QoS) parameter values can beefficiently scheduled and serviced with the aid of the integrated hardware Scheduler that supports up to four priority classes. The Scheduler uses calendartables to create arbitrary traffic schemes to a limit of 64K VirtualConnections.
The L64363's memory controller provides a glueless interface forasynchronous SRAMs, synchronous SRAMs, and synchronous DRAMs that are used forlocal memory, while also serving as a control interface for external physicallayer devices. In addition, the memory controller allows APU booting frombyte-wide or serial EPROMs.
The primary interface for the device is a 33 MHz, 32-bit wide PCI bus. Asthe bus master, the L64363 is able to autonomously access control and datastructures in system memory. As a bus slave, the device provides transparent access to local memory and to the internal cell buffer for external PCI busmasters. The PCI interface also implements four separate FIFOs to maximize theperformance of simultaneous read/write operations as bus master or slave.
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