ATM ChipWeb logo



New Chip



ATM Chip Database

  • Previous: SESAR
  • Up: List all categories

  • IGT (Integrated Telecom Technology ) : WAC-123-A

    155 Mbps Single-chip ATM Network Termination Adapter (SANTA) Processor

    The Single-chip ATM Network Termination Adapter (SANTA) Processor provides ATM Layer Segmentation And Reassembly (SAR) functionality along with a 155 Mbps PHY layer on the same part. The SANTA Processor provides an integrated solution for performing the SAR tasks required to communicate over an ATM network. The device translates packet-based data into 53-byte ATM cells, which are asynchronously mapped into a synchronous SONET/SDH payload. The SANTA Processor is ideally suited for equipment requiring an interface between packet-based data and ATM-based networks, such as ATM adapters, ATM switches, hubs, bridges, routers, and test equipment.Features are

    • Supports Available Bit Rate (ABR) per the ATM Forum ABR Specification (based on the Enhanced Proportional Rate Control (EPRC) algorithm in the ATM Forum Traffic Management Specification 4.0) to provide rate-based dynamic bandwidth allocation on a per-Virtual Channel (VC) or per-Virtual Path (VP) basis.
    • Supports Constant Bit Rate (CBR) traffic with rates set on a per-VC or per-VP basis.
    • Supports Unspecified Bit Rate (UBR) traffic with rates set on a per-VC or per-VP basis.
    • Supports software-assisted Variable Bit Rate (VBR) traffic with rates set on a per-VC or per-VP basis.
    • Directly supports ATM Adaptation Layer Five (AAL5) segmentation and reassembly.
    • Segments and reassembles data at a sustained rate of 155 Mbps.
    • Supports concurrent Operation, Administration, and Maintenance (OAM) cells, Resource Management (RM) cells, and AAL5 cells on each active connection.
    • Supports OAM transfers through the segmentation and reassembly of raw cells.
    • Supports simultaneous segmentation and reassembly of up to 4K active connections.
    • Supports scatter and gather packet capability for large packets.
    • Start Of Packet (SOP) offset available for ease of implementing bridging and routing among different protocols.
    • Provides a virtual Direct Memory Access (DMA) for each connection to segment and reassemble data directly to and from main memory across the Peripheral Component Interconnect (PCI) bus.
    • Provides a choice of two UNI formats and rates:
      • STS-3c/STM-1 rate (155 Mbps) in accordance with the ATM Forum SONET UNI Specification.
      • STS-1 (51 Mbps) in accordance with the ATM Forum SONET UNI Specification.
    • Provides built-in performance and alarm monitoring of SONET/SDH signals.
    • Provides boundary scan capability and tristatable outputs for ATE testing.
    • Supports eight UNI VP bits and six to nine VCs per VP.
    • Provides packet memory interface via an integrated 32-bit PCI bus interface.
    • Supports misaligned accesses over the PCI bus.
    • Contains a built-in 32-bit connection memory interface.
    • Provides a programmable connection memory size ranging from 32K x 32 (512 connections) to 128K x 32 (4K connections), based on the number of connections required.<\ul>

      Technology: unknown
      Package: unknown 0 Pin

      If you are the producer of this chip and want to correct/update the presented information, please feel free to register for direct database access.
ChipWeb Home

Last update: 14.11. 2009
Last link check: 01.03. 2006
All registered names and trademarks are the property of their respective owners.
No guarantee is given and no responsibility is taken for the information provided.
© 2024     Thomas Martin Knoll   Impressum   Datenschutz
back Kirche Reichenbach Vogtland