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    IGT (Integrated Telecom Technology ) : WAC-021-C

    AAL1 SAR Processor

    The AAL1 Segmentation And Reassembly (SAR) Processor (WAC-021-B) provides DS1 or DS3 line interface access to an ATM Adaptation Layer One (AAL1) Constant Bit Rate (CBR) ATM network. It arbitrates access to an external SRAM for storage of the configuration, the user data, and the statistics. The device provides a microprocessor interface for configuration, management, and statistics gathering. Features include

    • Provides AAL1 segmentation and reassembly of eight 2 Mbps data streams or one 45 Mbps or less data stream.
    • Supports 256 Virtual Channels (VCs).
    • Supports n x 64 structured data format.
    • Supports arbitrary VC mapping, including alternating time slots.
    • Provides Common Channel Signaling (CCS) and Channel Associated Signaling (CAS) configuration options.
    • Provides per-VC data and signaling conditioning in both the transmit and the receive directions.
    • Arbitrates a 16-bit processor interface to a 128K x 16 (15 ns) SRAM.
    • Supports multicast connections, ATM Monitoring (AMON), Remote Monitoring (RMON), and ATM Circuit Steering (ACS).
    • Provides per-VC transmit and receive queuing.
    • Provides a calendar queue service algorithm that produces minimal Cell Delay Variation (CDV).
    • Provides supervisory transmit and receive buffers for Operation, Administration, and Maintenance (OAM), and for ATM signaling.
    • Generates pointers for structured data transmission.
    • Provides sequence number and sequence number protection generation.
    • Provides partially filled cell generation with the length configurable on a per-VC basis.
    • Generates and transmits Synchronous Residual Time Stamp (SRTS) values.
    • Provides an ATM-layer UTOPIA interface.
    • Provides per-VC CDV tolerance settings.
    • Provides per-VC partially filled cell length settings.
    • Provides processor interrupts for OAM cell receptions.
    • Provides a multiplexed interface to external receive Phase Locked Loops (PLLs) for SRTS clock recovery.
    • Counts invalid Cyclic Redundancy Check (CRC) values for sequence numbers.
    • Counts OAM cells.
    • Counts dropped OAM cells.
    • Counts data cells transmitted per VC.
    • Counts conditioned data cells transmitted per VC.
    • Counts cells not transmitted due to line resynchronizations per VC.
    • Counts cells received per VC.

    Technology: unknown
    Package: unknown 0 Pin

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