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Quad SONET ATM UNI Processor
The ALC-ATM-106 Quad SONET UNI Processor is a synthesizable core in Verilog HDL
provides SONET framing for four independent channels. It implements the SONET/SDH
processing and ATM cell mapping functions at OC1 or OC3 rates. Each channel consists of
Transmission Convergence and Cell Delineation Block. The transmission convergence
implements SONET/SDH processing that conforms to ATM forum UNI 3.1 specification and
ATM physical layer for Broadband ISDN. The cell delineation block conforms to CCITT
recommendation I.432. On the drop side the processor provides ATM Forum's UTOPIA level
2 compliant interface. On the line side, each channel contains logic for Serial-to-Parallel
conversion. Each channel can be configured independently to operate at either OC1 or OC3
Key Features of the QUAD SONET UNI Processor
- Conforms to ATM Forum UNI 3.1 specification and ATM physical layer for
Broadband ISDN as per CCITT recommendation I.432.
- Operates at STS-1 or STS-3c data rates,. Transmit and receive sections operates
on bit serial data and are asynchronous to each other.
- Provides diagnostic, line, and timed loopback modes
- Provides ATM Forum's UTOPIA Level 2 compliant interface.
- Provides a generic 8-bit microprocessor bus interface for configuration, control and
- Capability to insert and extract generic flow control (GFC) bits via a serial interface.
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