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Interworking ElementFeatures include
- Single chip full duplex ATM packetizer / depacketizer for eight
E1/T1 highways
- All T1/E1 channels are independently configurable
- Structured and unstructured mode
- ATM cell mapping according to G.804
- AAL1 and optional AAL0 functionality
- Support for partially filled cells
- Multiport UTOPIA level 1 interface
- 16 bit microprocessor interface
- Built-in data path loops for test
- JTAG boundary scan test support
The IC is manufactured in 0.5 µm 3.3 V CMOS technology Technology.
Technology: | 0.5µ CMOS |
Package: | unknown 0 Pin |
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http://bv.sacosnet.de/pdf/1998-1999/GF_19/W_01_99.pdf
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