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  • AMCC (Applied Micro Circuits Corporation ) : S3011/3012

    SONET/SDH/ATM OC-3 Transmitter and Receiver

    The S3011/S3012 SONET/SDH transmitter and receiver chips are fully integrated serialization/deserialization SONET OC-3 (155.52 Mbit/s) interface devices. With architecture developed by the Pacific Microelectronics Centre (PMC), the chipset performs all necessary serial-to-parallel and parallel-to-serial functions in conformance with SONET/SDH transmission standards. The devices are also suitable for ATM applications. The figure below shows a typical network application.

    On-chip clock synthesis is performed by the high-frequency phase-locked loop on the S3011 transmitter chip allowing the use of a slower external transmit clock reference. Clock recovery is performed on the S3012 receiver chip by synchronizing its on-chip VCO directly to the incoming data stream. The S3012 also performs SONET/SDH frame detection. The chipset can be used with 19.44 MHz reference clocks, in support of existing system clocking schemes.

    The low jitter PECL interface guarantees compliance with the bit-error rate requirements of the Bellcore, ANSI, and ITU-T standards.
    Features include

    • Complies with ANSI, Bellcore, and ITU-T specifications
    • On-chip high-frequency PLL for clock generation and clock recovery
    • Supports 155.52 Mbit/s (OC-3)
    • Reference frequency of 19.44 MHz
    • Interface to both PECL and TTL/CMOS logic
    • 8-bit TTL/CMOS datapath
    • Diagnostic loopback mode
    • Lock detect
    • Low jitter PECL interface
    • < 2.5 Watt per set

    Documentation used to be available at:

    Technology: unknown
    Package: PQFP 80 Pin

    external WWW: Applied Micro Circuits Corporation : web page used to be available at:

    If you are the producer of this chip and want to correct/update the presented information, please feel free to register for direct database access.
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