The device is a UPC component based on leaky
bucket algorithm. It has two leaky buckets per
connection. The device has four input and four
output ports. The ports support the SAI and the
UTOPIA interface. Each input port is decoupled
from the rest of the chip through a four cell FIFO.
The component includes a 16 bit header translation.
16 k connections per link.
a universal Microprocessor interface
a single common static memory
four input links running on 155.52 Mbps
a single 16 bit output running at 50/40 Mhz
or four 8 bit outputs at 25/20 Mhz, UTOPIA tristate
2 port ID signals at the output port in case of
16 bit output
16 bit header translation
policing is done with the 'leaky bucket' algorithm