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    Advance (Advance Logic Corporation ) : ALC-ATM-101

    Sonet ATM UNI

    The ALC-ATM-101 UNI Processor is a synthesizable core in Verilog HDL for SONET framer that consists of Transmission Convergence and Cell Delineation Block with UTOPIA interface. On the line side the processor contains logic for Serial-to-Parallel conversion. Key Features

    • Conforms to ATM Forum UNI 3.1 specification and ATM physical layer for Broadband ISDN as per CCITT recommendation I.432
    • Operates at OC3 data rates, full duplex. Transmit and receive sections operates on bit serial data with independent clocks
    • Provides ATM Forum's UTOPIA Level 1 and Level 2 Multi PHY compliant interface
    • Provides a generic 8-bit microprocessor bus interface for configuration, control and status monitoring
    • Extracts ATM cells from the synchronous payload envelope using the cell delineation algorithm as per CCITT Recommendation I.432.
    • Descrambles cell payload. The descrambler can be optionally turned off.
    • Performs header error check sequence (HCS) with single bit error correction, and multibit error detection. Coset addition/subtraction is optional.
    • Filters idle/unassigned and errored cells. Filtering can be optionally turned off.
    • Detects out of cell delineation (OCD) and loss of cell delineation (LOC).
    • Counts received cells. Idle/Unassigned cells and errored cells are not counted.
    • Keeps count of cells with single and multibit errors.
    • Accepts byte serial data at OC-3 frame rates (155.52 Mbps). Bytes need not be aligned to octets in the frame.
    • STS-3c framing as per Bellcore TR-NWT-000253. Searches and locks to framing pattern bytes (A1, A2), and descrambles the received frames. Descrambler can be optionally turned off.
    • Detects loss of signal (LOS), out of frame (OOF), loss of frame (LOF), line alarm indication signal (LAIS), far end receiver failure (FERF), loss of pointer (LOP), path alarm indication signal (PAIS), path remote defect indication signal (PRDI).
    • Counts section BIP-8 errors (B1), line BIP-24 (B2) errors, line far end block errors (line FEBE), received path BIP-8 errors (B3), and path far end block errors (path FEBE).
    • Processes the pointer action bytes H1, H2, H3 as per Bellcore TR-NWT-000253. Interprets the received payload pointer (H1, H2), and extracts the synchronous payload envelope and path overhead.
    • Generates interrupts on alarm conditions. Interrupts are maskable.

    Technology: unknown
    Package: unknown 0 Pin

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