LSI (LSI Logic Corperation ) : L64363

ATMizer II

The ATMizer II Application-Specific Standard Product is ahighly integrated ATM segmentation and reassembly (SAR) engine optimized forinter-networking and native ATM applications. The L64363 supports full duplexTx/Rx operation at 155 Mbps (OC-3), and is the second generation device withinLSI Logic's ATMizer product family.

A primary feature of the ATMizer product family is the flexibility offered by the ATM Processing Unit (APU), which is based on an embedded MiniRISC CPU Core. The APU allows users to modify operation of the device, accommodate changes in ATM specifica-tions, and differentiate their products through software. The L64363 integrates the APU with other key functional blocks to offer networking equipment designers both a flexible and high-performance solution for their system needs.Features include

• Embedded MiniRISC CW4010 CPU
• Floating point arithmetic instructions
• Enhanced DMA (EDMA) SAR engine and DMA controller
• Transmit cell scheduler
• Local memory bus with integrated memory controller
• SRAM, SSRAM, SDRAM interfaces
• Multi-PHY UTOPIA Level II interface
• PCI bus interface
• Allows user to implement desired traffic managementschemes and modify device operation via software upgrades (industry standardMIPS-II compatible)
• Arithmetic instructions integrated within the APU allow implementation of ATM-Forum compliant Available Bit Rate (ABR) traffic management
• EDMA SAR functionality requires minimal support from APU, while DMA engine allows user to move CS-PDUs between host and local memory, and provides efficient buffer management
• Calendar based scheduler supports an arbitrary number of rates at a fine level of granularity
• Enables storage of VC descriptors, Buffer descriptors, user PDUs, andallows control of PHY devices via lower 8 bits
• Supports use of synchronous DRAM, and synchronous and asynchronous SRAM as local memory, for selecting optimum cost/performance levels
• Capability to support up to 24 PHY devices

The EDMA hardwired SAR functionality is optimized for AAL5 traffic, and assists the APU in segmentation and reassembly, and memory management tasks (support for AAL0, 1, 3/4, is also supported through APU assist).

Connections with different Quality of Service (QoS) parameter values can beefficiently scheduled and serviced with the aid of the integrated hardware Scheduler that supports up to four priority classes. The Scheduler uses calendartables to create arbitrary traffic schemes to a limit of 64K VirtualConnections.

The L64363's memory controller provides a glueless interface forasynchronous SRAMs, synchronous SRAMs, and synchronous DRAMs that are used forlocal memory, while also serving as a control interface for external physicallayer devices. In addition, the memory controller allows APU booting frombyte-wide or serial EPROMs.

The primary interface for the device is a 33 MHz, 32-bit wide PCI bus. Asthe bus master, the L64363 is able to autonomously access control and datastructures in system memory. As a bus slave, the device provides transparent access to local memory and to the internal cell buffer for external PCI busmasters. The PCI interface also implements four separate FIFOs to maximize theperformance of simultaneous read/write operations as bus master or slave.

Technology:	unknown
Package:	MQUAD 240 Pin