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CDRThe CDR VLSI device is a monolithic clock and data recovery component
that receives NRZ data, extracts the high-speed clock, and presents the
separated data and clock as its outputs. This device is designed
specifically for SONET OC12 and SDH STM4 applications at 622 Mbit/s.
The device contains a phase-locked loop (PLL) that generates a stable
622.08 Mbit/s reference clock output based upon an external 38.88 MHz
TTL reference clock input. The PLL is based on a VCO constructed from
integrated reactive components, which form a low-jitter/high-Q
differential tank circuit. Both frequency- and phase-detect circuitsreliably
acquire and hold lock in worst-case input jitter conditions
and scrambling patterns. The lock-detect circuitry signals when the CDR
acquires frequency lock. - Single-chip CDR circuit for 622 Mbit/s data
- Exceeds Bellcore and ITU jitter tolerance map requirements
- Single-ended ECL input has loop-through path for external 50 ohm
termination to minimize stubs and reflections
- Clock and data outputs are differential ECL
- External loop filter requires simple passive network
- Maintains clock in absence of data
- Can be used with a high-speed external clock
Technology: | unknown |
Package: | unknown 0 Pin |
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