IBM (IBM Microelectronics ) : ATM Transmitter Chip

The Transmitter chip passes outgoing data to the PHY layer. Like the Receiver chip, it is fully pipelined. It stores cells once only in external SRAM to facilitate traffic shaping. The chip can monitor performance on up to 16 connections at one time.The ATM Transmitter Chip provides the following functions:

• Runs at 622 Mbps (OC-12c)
• Cell Processing - Places cells in appropriate queues depending on their type (normal or OAM) and updates the VPi/VCi fields. It also performs per VP/VC queueing. Cells are admitted based on programmable two-level thresholds that are set per queue.
• Queue Memory Management - Logically divides the external SRAM into 16,000 queues with a shared memory architecture. Mapping of connections to logical queues is configurable. Memory management is performed completely in hardware.
• HEC Calculation - Calculates and inserts a new HEC value in each cell. It can be turned off if the PHY layer performs error detection and correction.
• Traffic Shaping - For each logical queue, determines when it is time to transmit a cell to the PHY layer.
• Multicast Handling - Supports multicasting for n...1 sources to 1...n destinations (n = 16,000).
• AAL5 Segmentation - Performs AAL5 segmentation for OAM cells as well as frames, completely in hardware. Control traffic may be inserted from the microprocessor.

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