ATM ChipWeb logo

 

Chips
NICs
Links

New Chip
New NIC

Register
Login

About

ATM Chip Database


  • Previous: ATM-POL2 Quad UPC power
  • Up: List all producers
  • Next: ATM-SHAP3 32 Class traffic shaper

  • Atecom (ATecoM GmbH ) : ATM-POL3

    Cell Input Flow Processor

    The device is a UPC component based on leaky bucket algorithm. It has two leaky buckets per connection. The device has four input and four output ports. The ports support the SAI and the UTOPIA interface. Each input port is decoupled from the rest of the chip through a four cell FIFO. The component includes a 16 bit header translation. Features are

    • 16 k connections per link.
    • a universal Microprocessor interface
    • a single common static memory
    • four input links running on 155.52 Mbps
    • a single 16 bit output running at 50/40 Mhz or four 8 bit outputs at 25/20 Mhz, UTOPIA tristate
    • 2 port ID signals at the output port in case of 16 bit output
    • 16 bit header translation
    • policing is done with the 'leaky bucket' algorithm

    Technology: unknown
    Package: PQFP 208 Pin


    If you are the producer of this chip and want to correct/update the presented information, please feel free to register for direct database access.
ChipWeb Home

Last update: 14.11. 2009
Last link check: 01.03. 2006
All registered names and trademarks are the property of their respective owners.
No guarantee is given and no responsibility is taken for the information provided.
© 2024     Thomas Martin Knoll  knoll@chipweb.de   Impressum   Datenschutz
back Kirche Reichenbach Vogtland