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ATM Chip Database |
- Previous: ATM-POL1 UPC Coprocessor
- Up: List all producers
- Next: ATM-POL3 Cell Input Flow Processor
- can operate in direct or lookup mode with up to 16k/64k connections per link.
- a universal Microprocessor interface
- a single common static memory
- four input links running on 155.52 Mbps
- policing is done with the \'leaky bucket\' algorithm
Atecom (ATecoM GmbH ) : ATM-POL2 |
Quad UPC power
The device is a UPC component based on leaky bucket algorithm. It has one leaky bucket per connection that can be cascaded to two. The device has four input and four output ports compatible to SAI and UTOPIA. Each input port is decoupled from the rest of the chip through a four cell FIFO. Features are
| Technology: | unknown |
| Package: | PQFP 208 Pin |
If you are the producer of this chip and want to correct/update the presented information, please feel free to register for direct database access.
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Last update:
14.11. 2009
Last link check: 01.03. 2006 |
All registered names and trademarks are the property of their respective owners. No guarantee is given and no responsibility is taken for the information provided. © 2024 Thomas Martin Knoll knoll@chipweb.de Impressum Datenschutz |
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