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622 Sonet ATM UNI
The CD block during receive, extracts the ATM cells from the synchronous payload envelope
using HEC based cell delineation algorithm as per CCITT I.432 recommendation. The CD
block performs a single bit error correction and multibit error detection. Idle/unassigned cells
may be dropped by programming appropriate bits in the control registers. Cells with multibit
errors are dropped. Single bit and multibit errors, and passed cells are accumulated for
performance monitoring purposes. The ATM cell payloads are descrambled and are written
into an internal programmable-length 4-cell FIFO.
The CD block during transmit, inserts ATM cells into the synchronous payload envelope by
extracting the cells from an internal programmable-length 4-cell FIFO. It computes and
inserts the HEC value in the cell headers. If a complete cell is not available for transmit,
idle/unassigned cells are automatically inserted into the transmit stream. The cell payload can
be optionally scrambled under register control.
There are three interfaces to the device:
Key Features of the Device:
- 16 bit UTOPIA interface to the ATM layer clocked at 40 MHz
- Microprocessor interface for control and status clocked at 33 MHz
- 16 bit line interface to the physical media clocked at 40 MHz
- Supports ATM User-Network Interface at 622 Mbps (STS-12c/STM-4).
- Implements ATM Forum UNI specification and ATM physical layer for B-ISDN according to CCITT recommendation I.432
- Processes full duplex 622 Mbps, or 155 Mbps, or 51 Mbps data streams via a 16 bit parallel interface..
- Provides ATM Forum's UTOPIA interface with FIFO buffering to the ATM layer
- Provides a generic 8-bit microprocessor bus interface for configuration, control and status monitoring
- Provides support for diagnostics and debug
Technology: || unknown|
Package: || unknown 0 Pin|
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