- Previous: ATM Segmentation and Reassembly Device
- Up: List all categories
- Next: SARA-Lite
The STAF VLSI device is a SONET/SDH transceiver and framer.
It combinesmultiplexing, demultiplexing, SONET/SDH framing, clock synthesis PLL,and loopback functions in a single monolithic integrated circuit.Implementation with the STAF requires only a simple external RC loopfilter and standard TTL and ECL power supplies. For optimalperformance, the STAF is packaged in a 68-pin multi layer ceramic (MLC)surface-mount package with an integral CuW heat spreader. The STAFprovides physical interfaces for STS12/STM4 (622.08-Mbit/s) orSTS3/STM1 (155.52-Mbit/s) SONET/SDH systems.The STAF meets ANSI, Bellcore, and ITU requirements for a SONET/SDHdevice. With a 51.84-MHz reference clock, the phase-locked loop (PLL)provides 77.76MHz or 19.44-MHz output for the multiplexer and 77.76MHzor 19.44MHz and 51.84-MHz output for the demultiplexer.
- Byte-parallel multiplexing, demultiplexing, framing, and clock synthesis PLL in one device
- Choice of STS12/STM4 or STS3/STM1 transmission rates
- Configurable master or slave reference clock generation and PLL bypass for external clocking
- 77.76 or 19.44-MHz output for the multiplexer and 77.76 or 19.44-MHz and 51.84-MHz output for the demultiplexer
- External RC loop filter
- Pass-through mode and three loopback modes for enhanced field diagnostics
- Frame-synchronous and byte-aligned demultiplexer output, according to SONET/SDH framing standards
- Search, detect, and recovery of framing on out-of-frame (OOF) input
- Standard TTL and differential or single-ended ECL I/O (except TXCK)
- Tristate TTL output for factory circuit-board testability
- Dual-supply operation (+5V, -5.2V)
- Low power dissipation (1.9W nominal)
The part is packaged in 68-pin surface-mount package with integral heats.
Technology: || unknown|
Package: || unknown 0 Pin|
If you are the producer of this chip and want to correct/update the presented information, please feel free to register for direct database access.