DSL ChipWeb logo

 

Chips
Modems/NICs
Links

New Chip
New Modem/NIC

Register
Login

Guestbook
News Letter

Forum

MP4 Videos
zum DSL-Test


Forum
About
?>

DSL Chip Database


  • Previous: G.lite and G.dmt Analog Front End
  • Up: List all categories
  • Next: G.lite Analog Front End

  • LSI (LSI Logic Corperation ) : SpeedREACH DPS8002

    Dual channel AFE: full rate and G.lite

    LSI Logic - SpeedREACH DPS8002 The SpeedREACH DPS8002 is a collection of 2 Analog Front Ends (AFE) for G.dmt (full-rate) or G.lite ADSL operation in a small 12 mm X 12 mm 80-pin package for central office (CO) equipment.
    Features
    • ADSL CO AFE with two full RX and TX analog signal paths (excluding POTS reject filter and high-voltage line drivers/receivers)
    • Fully monolithic: minimal external components required (2 precision resistors, 4 non-critical resistors, and decoupling capacitors)
    • Compatible with ITU G.992.1 (G.dmt) and G.992.2 (G.lite) standards
    • Upstream RX channel: support for both 138 kHz and 276 kHz (for ADSL over ISDN)
    • Downstream TX channel: support for both 552 kHz (G.lite) and 1.104 MHz (G.dmt)
    • 14-bit linear 1.104 MS/s ADCs and 14-bit linear 4.416 MHz DACs
    • 4th-order low-pass filters for RX/TX paths, with ± 5% cutoff frequency accuracy
    • Programmable gain stages and attenuators in RX and TX paths
    • Receive path noise PSD: <-150 dBm/Hz
    • Integrated wakeup detector (no DSP needed for wakeup) supporting both G.hs (G.994.1) and legacy ANSI T1E1.413 Issue 2 wakeup protocols
    • Power: 800 mW max (both channels operating, full-rate mode)

    Documentation used to be available at:
    http://www.lsilogic.com/products/adsl/central_office.html

    Technology: ADSL
    Package: unknown 0 Pin
    Linux support: No


    external WWW: LSI Logic Corperation : http://www.lsilogic.com/products/adsl/central_office.html web page used to be available at: http://www.lsilogic.com/products/adsl/central_office.html


    external PDF: LSI Logic Corperation : http://www.lsilogic.com/techlib/marketing_docs/ADSL/dps8002pb.pdf PDF documentation used to be available at: http://www.lsilogic.com/techlib/marketing_docs/ADSL/dps8002pb.pdf
    If you are the producer of this chip and want to correct/update the presented information, please feel free to register for direct database access.
ChipWeb Home

Last update: 14.11. 2009
Last link check: 01.03. 2006
All registered names and trademarks are the property of their respective owners.
No guarantee is given and no responsibility is taken for the information provided.
© 2017     Thomas Martin Knoll   knoll@chipweb.de
100G Ethernet
Next Generation SDH
BGP-QoS.org
Life Cycle Costing (LCC)
back Kirche Reichenbach Vogtland Life-cycle cost (LCC) calculations