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ADSL Analog Front End
Burr-Brown's Analog Front-End from Texas Instruments reduces the size and
cost of an ADSL-compliant system by providing the active analog circuitry
needed to connect an ADSL Digital Signal Processor (DSP) to an external line
driver, receiver, TX/RX filters, hy-brid, transformer, and POTS filter. The
AFE1302 is designed for downstream data rates of 4Mbps and higher, and operation
at a clock rate of 35.328MHz, with an output word rate of up to 8.832MWords/s.
Functionally, this unit consists of a transmit (TX) channel, a receive
(RX) channel, a VCXO (Voltage Controlled Crystal Oscillator) control Digital-to-Analog
Converter (DAC), and VCXO active circuitry. The TX section converts, filters,
and buffers outgoing Discrete Multi Tone (DMT) data from the ADSL DSP. The
receive section amplifies, filters, and digitizes the DMT data received on
the twisted pair line. This IC operates on a single 5V supply. The digital
circuitry in the unit can be connected to a supply voltage ranging from 3.3V
to 5V. The chip uses only 570mW.
The AFE1302 is designed to be used with external amplifiers and filters
for noise reduction and dynamic-range improvement.
The RX channel consists of a low-noise PGA, a switched capacitor low-pass
filter, and fourth-order delta-sigma Analog-to-Digital Converter (ADC). The
delta-sigma modulator operating at a 32X oversampling ratio produces a 16-bit
output at word rates up to 8832kHz.
The TX channel consists of a fourth-order delta-sigma DAC, switched-capacitor
low-pass filter, programmable attenuator, and buffer. The buffer drives off-chip
into a low-noise line driver configured as a 3-pole active filter to produce
an overall low-noise high-drive TX output signal on a twisted pair line.
- NOISE FLOOR: -144dBm/Hz
- MULTIRATE COMPATIBLE
- VCXO CIRCUITRY AND DAC
- 8.8M TO 1.1MWords/s WORD RATE
- FIVE GENERAL-PURPOSE OUTPUTS
- 570mW POWER DISSIPATION
Package: ||TQFP 48 Pin|
Linux support: || No |
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