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- Quad channel ATM OC-3c (155 Mbit/s) PHY.
- Provides on-chip clock and data recovery and clock synthesis.
- Exceeds Bellcore-GR-253 jitter tolerance and transmit jitter requirements.
- Provides a generic 8-bit microprocessor interface for device control and register access.
- Provides standard IEEE 1149.1 JTAG test port for boundary scan.
- SONET Receiver
- Recovers clock and data.
- Frames to and decrambles recovered stream.
- Filters and captures Automatic Protection Switch bytes (K1,K2) and detects APS byte failure.
- Detects signal degrade and signal failure threshold crossing alarms.
- Captures and debounces synchronization status byte (S1).
- Counts received section BIP-8 (B1), line BIP-24 (B2), and path BIP-8 (B3) errors, and line and path FEBEs.
- Detects LOS, OOF, LOF, LAIS, LRDI, LOP, PAIS, PRDI and PERDI.
- Provides individual divide by 8 recovered clocks for each channel.
- Provides individual 8 KHz receive frame pulses for each channel.
- SONET Transmitter
- Synthesizes the 155.52 MHz transmit clock from a 19.44 MHz reference.
- Provides a single transmit frame pulse input to align the transport frames to a system reference.
- Provides single transmit clock as timing reference for transmit outputs.
- Inserts register programmable APS (K1, K2) and synchronization status (S1) bytes.
- Inserts PAIS, PRDI, LAIS and LRDI.
- Scrambles transmit data stream.
- ATM Processor
- Implements the ATM Forum User Network Interface Specification
- Inserts and extracts ATM cells into and from the SONET SPE.
- Performs cell payload scrambling and descrambling.
- Provides a UTOPIA Level II compliant system interface.
- Provides synchronous 4 cell transmist and receive FIFO buffers.
Package: || unknown 0 Pin|
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