Synergys SY69712 physical layer processor contains a fully-integrated serialization/de-serialization SONET OC-12 (622 Mbps) interface circuit. The device performs all necessary serial-to-parallel and parallel-to-serial conversations per SONET and SDH standards. on-chip clock generation is performed by a PLL allowing use of a 51.84 MHz clock as reference. Clock recovery is performed by synchronizing the on-chip VCO directly to the incoming data stream. The SY 69712 can also perform SONET/SDH frame detection and alignment on the input data stream.