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  • Previous: WAC-188-A ATM Switch Element
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  • IGT (Integrated Telecom Technology ) : WAC-413-A

    Quadzilla

    The WAC-413-A SONET ATM QUAD UNI Processor maps ATM cells asynchronously intofour synchronous SONET/SDH payloads via a 16-bit, 50 MHz UTOPIA Level 2 Version0.8 compliant interface. The UTOPIA interface, which can also be configured to be eight bits wide, is address mapped, via a 16-bit microprocessor port, toenable multiple WAC-413s to be dotted onto a single UTOPIA interface withoutany additional hardware. Four 2-cell FIFOs buffer the data between the UTOPIAinterface and the SONET/SDH interface. Before the ATM cells reach the serialinterface they are framed with either SONET or SDH overhead bytes followingSTS-1, STS-3c, or STM-1 format. Error insertion, HEC generation, scrambling,null cell generation, and cyclic GFC halt bit insertion into the transmit datastream may be optionally controlled. Via a software controlled enable bit, thefour transmit channels can be tied to the same UTOPIA address to provide abroadcast mode of operation. In the receive direction, four additional 2-cellFIFOs buffer the data heading to the UTOPIA interface. The SONET/SDH framing isstripped after being monitored for errors and status. Various counters, controlbits, and error detection logic cause mask able interrupts which keep themicroprocessor apprised of the current receive status. Twenty-bit messagecounters and 16-bit error counters, which interrupt on roll over, provide aneasy software interface for performance management. For applications thatrequire a backup connection, hardware hooks exist for software to implement APSas defined in Bellcore TR-NWT-000253. Features include

    • Maps ATM cells into four independent SONET/SDH channels in accordance with the ATM Forum's SONET UNI specification, version 3.1.
    • Operates at the STS-3c/STM-1 rate (155.52 Mbps), and the STS-1 rates (51.84 Mbps, 25.92 Mbps, 12.96 Mbps).
    • Adheres to the UTOPIA (Universal Test and Operations for ATM) agreement.
    • Transfers ATM data through an 8-bit or 16-bit, 50 MHz FIFO interface.
    • Implements MPHY cell-level handshake on the UTOPIA interface for four independent SONET/SDH channels.
    • Provides mappable MPHY layer that allows up to 31 separate channels on a single UNI interface using eight WAC-413s in parallel.
    • Provides software programmable broadcast transmit mode.
    • Transfers SONET/SDH-formatted data through four synchronous serial Non-Return to Zero (NRZ) interfaces.
    • Provides a 16-bit microprocessor port for configuration, status reporting, and individual alarm processing.
    • Provides 20-bit message counters and 16-bit error counters. All counters interrupt on roll over and can be optionally reset when latched. All counters for a given channel are latched simultaneously.
    • Provides built-in performance and alarm monitoring.
    • Provides self-test capability through built-in error generation and loopback.
    • Provides a bypass mode for transmitter to output a repeated 1-byte pattern for wave shape testing.
    • Provides hardware assistance for software implementation of Automatic Protection Switching (APS), via K1, K2 bytes.
    • Implements Generic Flow Control (GFC) halt function in accordance with ITU Recommendations I.150 and I.361.
    • Provides external lock/loss signal for interfacing to external transceiver.
    • Provides differential Pseudo Emitter Coupled Logic (PECL) serial signals.
    • Provides 3.3 V internal logic with 5 V tolerant, TTL compatible I/O.
    • Provides boundary scan capability and tristatable outputs for ATE testing.

    Technology: unknown
    Package: PQFP 208 Pin


    If you are the producer of this chip and want to correct/update the presented information, please feel free to register for direct database access.
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