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ATM Quad Routing Table
The QRT is an advanced communications
device supporting large, high performance
ATM systems. Its support of per-Virtual
Channel (VC) receive queues and 16 traffic
classes allows systems built with the QRT
to support sophisticated network service
offerings.The QRT supports architectures
from 800 Mbps to 320 Gbps, including a
stand-alone 800 Mbps switch mode.
Per-VC receive queues and two forms of
switch fabric Negative Acknowledgment
congestion indication (NACK) prevent
head-of-line blocking. The QRT supports
a multi-service class extension of the
Explicit Rate Indication for Congestion
Avoidance (ERICA+) algorithm for superior
Available Bit Rate (ABR) support. It also
provides five separate congestion thresholds,
each with hysteresis, that selectively control
AAL5 early packet discard and/or Cell Loss
Priority (CLP)-based cell dropping for
Unspecified Bit Rate (UBR) support. The
QRT provides a connection between a
UTOPIA Level 2 interface and a switch
fabric composed of IgT WAC-188 ATM
Switch Elements and/or IgT WAC-488
ATM Quad Switch Elements (QSEs).
- Provides for weighted, bandwidth controlled service of 16
- Provides per-VC, per-service class, per-same service
class, per-virtual output, and per-device congested queue
- Provides per-VC, per-service class,
per-same service class, per-virtual output, and per-device
maximum queue depth limits.
- Maintains 16 service classes.
- Provides round robin servicing of queues within each
priority with support for two forms of switch fabric NACK.
- Provides 31 virtual outputs.
- Maintains 16 service classes with per-VC
accounting for each virtual output.
- Executes a multi-service class extension of the ERICA+ algorithm developed at Ohio State University for ABR traffic.
- Supports early packet discard for UBR traffic and as a backup for ABR traffic.
- Supports CLP-based cell discard.
- Supports all 12 Virtual Path (VP) and 16 VC bits through the use of a double indirect lookup table.
- Performs header translation at both the input and the output directions. The input header translation is used to pass the output queue channel number through the switch.
- Supports multi cast with a superior queue-clearing multi cast algorithm for both the receive and transmit directions.
- Checks the parity of the header.
- Counts tagged cells.
- Checks for liveness of signal lines.
- Generates and traps cells.
- Counts cells transmitted.
- Counts cells dropped.
- Supports the external collection of enhanced statistics through a synchronous statistics interface.
- Provides four switch element interfaces with phase aligner. The phase aligner allow for external serialization of the data stream and allow for systems to be built with shelves up to 10 meters apart.
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