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155 Mbps ATM SAR controller for PCI based networking
The IDT77211 NICStAR(TM) is a member of IDT's family of products for Asynchronous
Transfer Mode (ATM) networks. The NICStAR performs both the ATM Adaption
Layer (AAL) Segmentation and Reassembly (SAR) function and the ATM layer protocol
A Network Interface Card (NIC) or internetworking product based on the
NICStAR uses host memory, rather than local memory, to reassemble Convergence
Sublayer Protocol Data Units (CS-PDUs) from ATM cell payloads received from
the network. When transmitting, as CS-PDUs become ready, they are queued
in host memory and segmented by the NICStAR into ATM cell payloads. From
this, the NICStAR then creates complete 53-byte ATM cells which are sent
through the network. The NICStAR's on-chip PCI bus master interface provides
efficient, low latency DMA transfers with the host system, while it's UTOPIA
interface provides direct connection to PHY components used in 25.6 Mbps to
155 Mbps ATM networks.
- Full-duplex Segmentation and Reassembly (SAR) at 155 Mbps "wire-speed"
(310 Mbps aggregate speed).
- Performs ATM layer protocol functions.
- Supports AAL5, AAL3/4, "AAL0" and "Raw Cell" formats.
- Supports Constant Bit Rate (CBR)Variable Bit Rate (VBR) and Unassigned
Bit Rate (UBR) service classes.
- Reassembles received CS-PDUs directly into host memory.
- Two buffer pools for independant or chained reassembly
- Segments CS-PDUs ready for transmission directly from host memory.
- PCI bus master interface for efficient, low latency DMA transfers with
- Operates with ATM networks up to 155.52 Mbps.
- Up to 16K open transmit connections.
- Up to 16K simultaneous receive connections.
- Glue-less integration to host system's PCI bus.
- UTOPIA Interface to PHY.
- Utility & Management Interface to PHY.
- Standalone controller: embedded processor not required.
- Supports high-performance, lowest-cost ATM NIC solution.
- Supports Big/Little endian on PCI interface
Package: ||PQFP 208 Pin|
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