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  • Previous: CY 7B951 SONET/SDH Serial Transceiver
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  • Cypress (Cypress Semiconductor ) : CY 7B952

    SONET/SDH Serial Transceiver

    The SONET/SDH Serial Transceiver (SST) is used in Wide Area Network (WAN) SONET/SDH and ATM applications to recover clock and data information from a 155.52-MHz or 51.84-MHz NRZ or NRZI serial data stream and to provide differential data buffering for the Transmit side of the system.

    Features are

    • Fully compliant with Bellcore and CCITT (ITU) specifications on:
    • Jitter Generation (<0.01 UI)
    • Jitter Transfer (<130 kHz)
    • Jitter Tolerance
  • SONET/SDH and ATM Compliant
  • Compatible with PMC-Sierra PM5343
  • Clock and data recovery from 51.84- or 155.52-MHz datastream
  • 155.52-MHz clock multiplication from 19.44-MHz source
  • 51.84-MHz clock multiplication from 6.48-MHz source
  • 1% frequency agility
  • Line Receiver Inputs: No external buffering required
  • Differential output buffering
  • 100K ECL compatible I/O
  • No output clock \"drift\" without data transitions
  • Link Status Indication
  • Loop-back testing
  • Single +5V supply
  • 24-pin SOIC
  • Compatible with fiber-optic modules, coaxial cable, and twisted pair media
  • Power-down options to minimize power or crosstalk
  • Low operating current: <65 mA

The IC is manufactured in 0.8 m BiCMOS Technology.

The part is packaged in 24 pin SOIC.

Documentation used to be available at:
http://www.cypress.com/cypress/prodgate/datacom/cy7b952.html and
http://www.cypress.com/pub/datasheets/38-02018.pdf

Technology: 0.8 BiCMOS
Package: PLCC 24 Pin


external WWW: http://www.cypress.com/portal/server.pt?space=CommunityPage&control=SetCommunity&CommunityID=209&PageID=259&fid=28&rpn=C

external PDF: http://www.cypress.com/portal/server.pt/gateway/PTARGS_0_2_1524_209_259_43/http%3B/sjapp20.mis.cypress.com%3B7001/publis


If you are the producer of this chip and want to correct/update the presented information, please feel free to register for direct database access.
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