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  • Previous: ATM-POL1 UPC Coprocessor
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  • Atecom (ATecoM GmbH ) : ATM-POL2

    Quad UPC power

    The device is a UPC component based on leaky bucket algorithm. It has one leaky bucket per connection that can be cascaded to two. The device has four input and four output ports compatible to SAI and UTOPIA. Each input port is decoupled from the rest of the chip through a four cell FIFO. Features are

    • can operate in direct or lookup mode with up to 16k/64k connections per link.
    • a universal Microprocessor interface
    • a single common static memory
    • four input links running on 155.52 Mbps
    • policing is done with the \'leaky bucket\' algorithm

    Technology: unknown
    Package: PQFP 208 Pin


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