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  • MMC (MMC Networks Inc. ) : ATMS2000

    ATM Switch Chipset

    MMCs ATMS2000 ATM Switch Engine implements the complete core functionality of a high performance ATM switch, optimized for work group and LAN backbone applications. The Switch is based on MMCs patented ViXTM technology. It offers an extremely low-cost highly-integrated solution, with all the switching functions performed by the chip set. The chip set consists of 4 chips. A total number of 9 chips are needed to implement the complete switch functions of a 16 x 16 155-Mbps-port switch; a total of 16 chips are needed to implement a 32 x 32-ports switch. The only additional components needed to complete the switch are low speed SRAMs, control processor, and standard PHY interface circuitry. The ATMS2000 chip set consists of four components:

    • ATMS2001: Memory Access Buffer (MBUF)
    • ATMS2002: Port Interface (PIF)
    • ATMS2003: Switch Controller 1 (SWC1)
    • ATMS2004: Switch Controller 2 (SWC2)
    A 32-port switch configuration requires one each of the SWC1 and SWC2 chips, six MBUF and eight PIF chips. A 16-port switch configuration requires one each of the SWC1 and SWC2 chips, three MBUF and four PIF chips.The core switch has the following features:Complete switch engine: all the switching functions are performed by the chip set
    • Non Blocking
    • Configurable as either thirty-two 155-Mbps ports, or sixteen 155-Mbps portsEvery four ports may be grouped to form one 622-Mbps port
    • Each 155 Mbps port may be divided into three 52-Mbps ports, or into six 25-Mbps ports
    • Up to 64K cells total buffering, dynamically allocated (more than 10,000 per port effective buffering)
    • Four queues for each 155 Mbps output port, for four levels of priority traffic
    • Both VP and VC switching capabilities
    • Supports up to 32K input VCs and 32K output VCs with on-chip addressing.
    • Expandable to unlimited number
    • Supports multicast
    • Dedicated CPU port for management and control
    • Hooks for external per VC processing (AAL-5 PDU discard, traffic management, policing, accounting, etc.)
    • Standard UTOPIA interface to the PHY module
    • Snooping capability on the activity of any port (by mirroring to one specific port)
    • Requires inexpensive 20ns SRAMs
    • 25 MHz operation
    The Switch is based on a shared memory architecture. ATM cells received by an input port are split into data payload and header. The data payload portion of the cell is transferred by the Port Interface (PIF) through the Memory Access Buffer (MBUF) to the Common Data Memory, while the header is transferred by the PIF to the Switch Controller (SWC). The SWC is responsible for the memory address generation and for the outgoing cell header generation.The complete Bill of Materials (excl. PHY) of a 32 port, 5 Gbps ATM switch, with 32K Cells total buffering (>5.6K Cells/port) is as follows:Core Components for 2,000, SRAM for 170, CPU for 300, PC Boards for 200,Enclosure + Power Supply for 300, Assembly Test for 80. This is a total of 3,050 (95/port).

    Technology: unknown
    Package: unknown 0 Pin


    If you are the producer of this chip and want to correct/update the presented information, please feel free to register for direct database access.
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