A maximum internal cell length of 64 bytes has been chosen. Each of the 16 input and output ports has a maximum speed of 400 Mbps which results in a total aggregate data rate of 6.4 Gbps per single chip.
A unique feature of the switching element is its scalability. For instance, switch systems with a larger number of ports can be built from the basic module as single- or multi-stage self routing network. In addition, the system port speed can be increased by connecting several modules in parallel. Plus better throughput for bursty traffic environments (LANs) can be achieved by increasing the size of the internal packet buffer or using paralleled modules.
Because of its modular architecture, 16 x 16 Switch-on-a-Chip is the ideal basis for a wide range of products with different price and performance demands.The 16 x 16 Switch-on-a-Chip includes:
Switches with a larger number of ports than the basic switch module can be realized by connecting several 16 x 16 Switch-on-a-Chip modules in parallel for a single-stage, or cascading them for a multi-stage system. 16 x 16 Switch-on-a-Chip has built-in logic to allow address-filtering at the input and activation of an output for supporting single-stage expansion. For multi-stage expansion every stage requires a different routing tag in general.
A unique feature of 16 x 16 Switch-on-a-Chip is to expand the actual speed of the switch ports by using multiple 16 x 16 Switch-on-a-Chip modules in parallel. Instead of an 8-bit wide port, the switch ports then become 16, or more bits wide, and a doubling, tripling etc. of the port speed is achieved.
The aggregate throughput of a packet switch is given by the product of all ports and the port speed. 16 x 16 Switch-on-a-Chip has the hardware control built-in to allow cascading the internal buffer memory of multiple 16 x 16 Switch-on-a-Chip modules, such that the system behaves as if it were one chip with increased buffer memory. Control signals between the 16 x 16 Switch-on-a-Chip modules provide proper packet sequence.
16 x 16 Switch-on-a-Chip has a built-in feature called link paralleling, which manages the bandwidth on such links fully with hardware. This means that 2 or 4 physical 16 x 16 Switch-on-a-Chip ports can be combined to support a double- or quadruple- speed link without software to control which connection is allocated to a physical 16 x 16 Switch-on-a-Chip output port.
The expansion methods can be combined freely to design a switch fabric. The port and performance expansion methods require the external manipulation of 16 x 16 Switch-on-a-Chip's control signal to provide maximum flexibility in functionality (e.g. port expansion can also be used to support multiple priorities).
16 x 16 Switch-on-a-Chip enables high speed communication networks that support applications featuring a heterogeneous mix of voice, data and video traffic. Typically such systems require the capability of handling multipoint connections for services such as video distribution and teleconferencing. 16 x 16 Switch-on-a-Chip provides a flexible multicast capability: it is possible to send a copy of a packet to all (broadcast) or only a subset (multicast) of the switch module’s output ports. In order to conserve buffer memory, only one packet storage location is used from which multiple copies are sent. The activation of a multicast connection is done through the packet routing header, and a dynamically programmable table internal to the 16 x 16 Switch-on-a-Chip module.
The part is packaged in 472 pin.
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