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SALI-25c - Six ATM Line Interface at 25 Mbit/s
The SALI-25C VLSI device is a controller for six 25.6 Mbit/s ATM Line Interfaces, with
a common 8-bit parallel transmit and receive UTOPIA interface on the terminal side.
It performs the transmission convergence function of six independent 25.6 Mbit/s
bit-serial line signals used for connection to private UNIs, and the terminal side
interface employs single cell I/O signals.
The device is designed to interface directly on the line side with PMD devices such
as the TranSwitch ALI-25T ATM Line Interface 25 Mbit/s Transceiver (part number
performs NRZI/NRZ conversion, serial to parallel conversion, 5B/4B code conversion,
data deserialization, 5B/4B decoding, descrambling, cell delineation, and idle byte
discard in the receive direction, and the inverse processes in the transmit direction.
The SALI-25C provides an 8-bit 33 MHz multi-PHY UTOPIA cell interface with ATM
The SALI-25C also provides a special UTOPIA mode for interfacing with the TranSwitch
CUBIT CellBus Switch (TXC-05801).
- Transmission Convergence
- meets ATM Forum specifications
- maps ATM cells to six 25.6 Mbit/s payloads
- NRZI/NRZ and 5B/4B conversions
- scambling, cell delineation and rate adaptation
- HEC generate/check with bad cell discard
- transmit GFC insertion for Xon/Xoff
- Line Interface
- six independent lines each with data and clock
- line rate at 32 Mbaud +/- 100ppm
- detects received illegal 5B codes
- direct interface to ALI-25T 5V transceivers
- idle signal generation on the line side
- single transmit clock input for all six line signals
- 8 kHz timing marker output
- 8-bit 33 MHz or UTOPIA Level 1 and 2 Interface
- single cell available cell level control
- 3 cells per line FIFO in the receive direction
- 2 cells per line FIFO in the transmit direction
- optional 4 priority queues per line sharing 2048 or 4096-cell external SRAM buffer for transmit
- Discarded, received and transmitted cell counts
- External memory (SRAM) interface
- External transceiver and LED controls
- Intel/Motorola processor interface with interrupts
- Test Access Port (IEEE 1149.1 boundary scan)
- Single +3.3 V, +/-5% power supply, 0.6W max.
Technology: || unknown|
Package: ||PQFP 208 Pin|
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