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  • Previous: LASAR 155 - ATM SAR and PHY Processor for PCI Bus
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  • Next: (NEASCOT-S20) 155M ATM INTEGRATED SAR CONTROLLER

  • Toshiba (Toshiba America Electronic Components ) : TC 35853

    TC 35853

    The TC35853F single-chip 155Mbps SAR chip for switch and hub applications is designed for User Network Interface (UNI) and Subscriber Network Interface (SNI) or a general packet relay interface. It also supports the standard UTOPIA interface and several vendor-specific interfaces for connecting to SONET/SDH-3c/ST1, DS3, E3, DS1, and E1 transmission links. Each data packet is segmented according to the AAL-type specified for that circuit and is placed on a linked-list cell queue in memory. It supports up to 1,023 circuits. The cell queues are served by a traffic shaper, which supports peak rate, sustained rate, minimum guaranteed rate, maximum burst size, priority level, CBR, variable bit rate, and best-effort quality of service (QoS) types. It supports Permanent Virtual Connections (PVC) and Switched Virtual Connections (SVC) and F4 and F5 operations administration and maintenance (OAM) flows. Digital's FLOWmaster* flow control is also supported as an option to provide zero cell loss, best-effort quality of service with increased reliability. It has full line-rate segmentation and reassembly for STS-3c link. The chip has an M6800C-style node processor interface and contains 20-bit addressing that supports a 1 megaword (64-bit) SRAM buffer. Designed and produced in 0.8 micron CMOS, the TC35853F has full scan and automatic test pattern generation (ATPG) for more than 97 percent fault coverage. It is offered in a 304-pin ceramic flat pack.

    Technology: unknown
    Package: CQFP 304 Pin


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