ATM ChipWeb logo

 

Chips
NICs
Links

New Chip
New NIC

Register
Login

Guestbook
News Letter

Forum
About

ATM Chip Database


  • Previous: TC 35853
  • Up: List all categories

    NEC (NEC ) : µPD98405

    (NEASCOT-S20) 155M ATM INTEGRATED SAR CONTROLLER

    NEC has concluded the development of its ATM controller as a commercial product harnessing on a single chip with a high speed communication capability of approx. 155Mbps to support the ABR (Available Bit Rate) service the ideal service for computer data transmission via ATM networks. With the use of a network interface card, the new product permits high-speed communication at approximately 155Mbps between personal computers and network stations. Its principal features include:

    • It is ideally suited for the ABR service as communication data rejection due to network crowding is reduced to a minimum achieving a dramatic improvement in data transmission efficiency;

    • Both the SAR (Segmentation and Reassembly) and PHY (Physical Layer) functions formerly requiring two chips have now been integrated on a single chip;

    • Its built-in 64-bit PCI bus interface can also be used on high-speed workstations;

    • It assists the LAN emulation function facilitating the configuration of ATM network while coping with the existing LAN environment.

    The products features the following main characteristics.

    (1) Built-in ABR function

    It provides hardware support for the ABR service class, the best service class for computer data communication. The ABR service class can alter the communication rate at any time in accordance with the feedback control using management cells. The new product is automatically executes, in hardware, all data reception and transmission of management cells and all consequent changes in the communication rate.

    (2)SAR and PHY functions harnessed on a single chip

    Whereas conventionally a two-chip configuration was required, the new product integrates the SAR and PHY functions on a single chip.

    1. The SAR function segments the data to be transmitted into blocks of a predetermined length, and fetches/assembles data from the data receiving cells.

    2. For transmission, the PHY function aligns the data that has been segmented into cell units with the frame of the data transmission system on the optical fiber and extracts these cells from the received frame.

    The merit of having both these function on a single chip is the compactness and low-cost efficiency resulting from this configuration.

    (3) Supporting both the 32-/64-bit PCI and general-purpose bus systems

    With the built-in PCI bus interface capable of handling high-performance work stations the new product supports the 32-/64-bit, 5/3.3V, 33MHz interface. It also supports a general-purpose bus interface (32-bit, 5/3.3V, 33MHz), and through the addition of a simple external circuit, it can also be connected to non-PCI buses such as S and AP buses as well as built-in general-purpose microcomputer buses.

    (4) LAN emulation assist function

    The new product supports the LAN emulation functions that are the standard for operating the existing LAN protocols in an ATM network. Various LAN emulation functions are supported in hardware in an attempt to upgrade performance by reducing high-end software processing for LAN emulation operation. This includes the filtering of receiving packets by destination address.

    (5) Supporting multi-cell burst transmission in data reception and transmission

    n the case of DMA transfer of received and transmitted data involving a host system memory, the product supports not only burst transfer of data corresponding to a single cell but also of data corresponding to multiple cells (multi-cell burst transfer for a maximum of up to 5 cells) in data reception/transmission. This results in a roughly 12% improvement in bus performance.

    (6) Built-in 96 cell data receiving FIFO

    Built-in FIFO processing of 96 cell of received data makes it possible to minimize receiving cell rejection even during local overcrowding at the terminals.

    Technology: 0.35µ CMOS
    Package: PQFP 304 Pin


    external WWW: http://www.ee.nec.de/applications/communication/z_products/assp/atm/upd98405.html

    external PDF: http://www.ee.nec.de/_pdf/S12689EJ3V0DS00.PDF


    If you are the producer of this chip and want to correct/update the presented information, please feel free to register for direct database access.
ChipWeb Home

Last update: 14.11. 2009
Last link check: 01.03. 2006
All registered names and trademarks are the property of their respective owners.
No guarantee is given and no responsibility is taken for the information provided.
© 2017     Thomas Martin Knoll  knoll@chipweb.de
100G Ethernet
Next Generation SDH
BGP-QoS.org
back Kirche Reichenbach Vogtland