ATM Segmentation and Reassembly Device
SARA II is a single-chip solution that performs complete segmentation and reassembly (SAR) for implementing low-cost ATM adapter cards, legacy LAN to ATM hubs, and routers. The device provides a PCI-based host interface to segment and reassemble packets directly in the host memory. In the transmit direction, the SARA II generates cells that conform to the ATM Forum traffic management service classes, such as CBR, VBR and ABR. Flexible traffic scheduling mechanisms support ABR traffic with associated RM cell processing. On the receive side, the SARA II allows simultaneous reassembly of over 64,000 connections directly in the host memory. The host buffers may be arbitrary sized blocks placed on arbitrary byte boundaries. An integrated SONET/SDH STS-1/STS-3c/STM-1 framer and overhead termination supports complete framing, cell delineation and cell rate decoupling functions. The UTOPIA interface supports connection to other line rates or ATM layer devices.
Documentation used to be available under:
web page used to be available at: http://www.transwitch.com/products/prodc_sara2.shtml
PDF documentation used to be available at: http://www.transwitch.com/products/prodc_sara2.shtml
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