The Receiver chip receives incoming
data from the PHY layer. It is fully
pipelined and stores cells in external
SRAM to reduce system cost. The ATM
Receiver Chip provides the following
Runs at 622 Mbps (OC-12c)
HEC Validation - Performs 2-bit
error detection and 1-bit error correction
on the ATM cell header. It can be turned off if the
PHY layer performs error detection and correction.
VPi/VCi Lookup - Uses the full 28-bit VPi/VCi fields
and line index to access an internally used index, while
the ATM cells move through the pipeline. Both UNI and
NNI cell types are supported.
Checks bandwidth used by incoming cells per
connection. It increments a counter when a cell
is discarded. One of six standard policing modes can
be selected per connection.
Management - Reassembles up to 62 AAL5 frames
simultaneously. Frames are selected transparently
from the total of 16,000 connections and are stored in
external SRAM that is organized as a 64-bit logical FIFO shared memory.
Buffer management is performed completely in hardware.
Control Traffic Extraction - Decodes and optionally copies or diverts AAL5 frames,
OAM cells, and other flows to the micro-processor. Performance monitoring c
an be selected for a total of 16 connections.
Switch Header Insertion - Inserts the routing header that the ATM switch
uses to determine the output port.
unknown 0 Pin
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