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  • Previous: PM 7346 S/UNI QJET four channel framer/processor
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  • Next: PM5349 (S/UNI-155-QUAD)

  • PMC (PMC Sierra Inc. ) : PM 7375

    LASAR 155 - ATM SAR and PHY Processor for PCI Bus

    • Combines PHY, ATM, AAL-5, and PCI DMA Controller on a single device to simplify the design, programming and manufacturing of ATM adapters.
    • Conforms to ATM Forum User-Network Interface (UNI) Specification Version 3.1, Bellcore Standard TA-NWT-001113 and ITU-T Recommendations I.432 and I.363.

      HOST INTERFACE

    • Provides a 32 bit, 33MHz Peripheral Component Interconnect (PCI) interface that is compliant with the PCI Local Bus Specifications Version 2.0 and supports both bus-master and bus-slave access modes. Other 32 bit system buses can be accomodated using external glue logic.
    • Implements an efficient DMA controller to manage the transfer of packets between the SAR engine and the host memory with minimum PCI Host intervention. There is no need for a local packet memory.
    • The transmit and receive DMA channels support scatter/gather capabilities where a packet can be stored in non-contiguous buffers.
    • Provides an 8 cell FIFO in the transmit direction and a 96 cell FIFO in the receive direction to allow for up to 270 s of PCI bus latency in the receive direction.

      PHYSICAL LAYER

    • Incorporates the industry standard PMC PM5346 S/UNI-LITE to provide SONET and SDH interfaces at STS-3c/STM-1 (155.52 Mbps) and STS-1 (51.84 Mbps) rates.
    • Provides on-chip clock recovery and clock synthesis units that are compliant with Bellcore TR-NWT-000253 Issue 2 and ITU-T G.958 jitter requirements.
    • Performs SONET/SDH framer, overhead and cell processing functions at STS-3c/STM-1 and STS-1 rates.

      ATM & ADAPTATION LAYERS

    • Supports the simultaneous segmentation and reassembly of 128 open virtual circuits (VCs) in both directions.
    • Provides leaky bucket peak rate enforcement using 8 programmable peak queues coupled with sub rate control on a per VC basis.
    • Implements sustainable cell rate (SCR) enforcement using a token generation mechanism on a per VC basis.
    • Provides an internal VC parameter storage for both the 128 transmit and 128 receive VCs to simplify the design of ATM adapter and to sustain a high data through-put rate.

      MULTIPURPOSE PORT

    • In bypass mode, provides an 8-bit SCI-PHY compliant port to connect to an external physical layer processor such as PMC PM7345 S/UNI-PDH.
    • In non-bypass mode, supports the insertion and extraction of CBR cells that carry encoded video and audio signals.

      MICROPROCESSOR INTERFACE

    • In slave mode, provides a generic 8-bit microprocessor port for the configuration, control, and monitoring by an optional microprocessor.
    • In master mode, allows for the control of two external devices without glue logic.

      PACKAGING

    • Provides a standard 5 signal P1149.1 JTAG test port for boundary scan board test purposes.
    • Implemented in low power, 0.6 micron, +5 Volt CMOS technology with TTL and pseudo ECL (PECL) compatible inputs and outputs.
    • Packaged in 208 pin plastic quad flat pack (PQFP) package.
    This part combines PHY, ATM, AAL-5 and PCI-DMA Controller on a single device to simplify the design, programming and manufacturing of ATM adapters. It provides a 32-Bit 33 MHz Peripheral Component Interconnect ( PCI) interface that is compliant with the PCI Bus spec Version 2.0. Features are
    • incorporates PMC PM5346 to provide SONET and SDH interfaces at 155.52 Mbps resp. 51.84 Mbps.
    • Provides on-chip clock recovery and clock synthesis units that are compliant with Bellcore s jitter requirements.
    • provides an 8 cell FIFO in the transmit direction and a 96 cell FIFO in the receive direction to allow for up to 270 mus of PCI latency in the receive direction.

    Technology: 0.65 Low Power CMOS
    Package: PQFP 208 Pin


    external WWW: http://www.pmc-sierra.com/products/details/pm7375/


    If you are the producer of this chip and want to correct/update the presented information, please feel free to register for direct database access.
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