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1.2G ATM SWITCH LSI (NEASCOT-X10)
The µPD98410 is targeted at ATM switches (line concentrators accommodating a number of 155.52- and 25.6-Mbit/s
lines) and routers. It has high-speed switching functions for directing fixed-length data (called ATM cells) received
from one line to another line, the latter being selected according to the header information in the cell.
- single-chip ATM switching functions (including header conversion), which were
previously realized using nine chips;
- a high-speed, non-blocking switching capacity of 1.2 Gbits supporting up to eight
- the connection of lines of multiple data transfer rates, enabling the switching of up
to 24 x 24 logical ports;
- four different QOS classes to support diversified multimedia application
communication, as well as built-in ABR traffic control and EPD control, that is useful
for increasing throughput; and,
- high-traffic performance shared buffer architecture, that enables the use of cell
buffers at high efficiency (that is, enabling the buffering of up to 51.2 k-cells).
- Compliance with ATM Forum UNI versions 3.1 and 4.0
- UTOPIA level 2 interface (8 bits, max. clock rate 40 MHz)
Information used to be available at:
Technology: ||0.35µ CMOS|
Package: ||BGA 580 Pin|
web page used to be available at: http://www.ee.nec.de/Centers/TCAC/atm/upd98410.html
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