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  • Previous: µPD98411 (NEASCOT-P40)
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    NEC (NEC ) : µPD98409

    NEASCOT-S40C

    The NEASCOT-S40C uses an internal controll memory for connection data and reduces therefore the number of ICs nessesary to implement a ATM NIC. Features are

    • Conforms to the ATM-Forum recommendations
    • Implements PCI bus interface (5V, 3.3 V, 32-bit, 33 MHz), rev. 2.1 compliant
    • Implements AAL-5 SAR sublayer and ATM layer
    • Supports up to 64 virtual channels with integrated control memory
    • Two traffic shapers for transmission scheduling
    • MPEG packet transfer engine to reduce transfer overhead of compressed picture data
    • Integrated 12-cell FIFO
    • PHY device interface: UTOPIA Level 1
    • JTAG boundary scan test function

    Technology: 0.35µ CMOS
    Package: PQFP 240 Pin


    external WWW: http://www.ee.nec.de/applications/communication/z_products/assp/atm/upd98409.html


    external PDF: NEC : http://www.ee.nec.de/_pdf/S12775EJ2V0DS00.PDF PDF documentation used to be available at: http://www.ee.nec.de/_pdf/S12775EJ2V0DS00.PDF
    If you are the producer of this chip and want to correct/update the presented information, please feel free to register for direct database access.
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