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Clock Recovery and Data Retiming IC
The MC2070 is an integrated clock recovery and data
retiming IC intended for high-speed fibre-optic based communications.
Using PLL techniques, an on-chip VCO is locked to an incoming
NRZ data stream, and both clock and retimed data signals are brought
out. Fully differential architecture and low noise design techniques
ensure excellent jitter & PSRR performance.
The PLL features dual control loops for frequency
and phase acquisition. The frequency loop acquires the input data
frequency, locking onto random or scrambled NRZ data without the
need for preamble. At frequency lock (i.e. zero frequency error)
this loop has no further effect. The phase control loop then works
to ensure that the output phase tracks the input phase. The clock
is locked 90 out of phase with the data for maximum jitter immunity.
Technology: ||0.8µ BiCMOS|
Package: ||DIP 16 Pin|
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