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Enhanced ATM Self Routing Switch Element
The SRE-L is an enhanced version of the SRE which is optimised for the LAN switching
The output buffers have been increased from 75 to 146 cells and additional capabilities
have been added to its Traffic Routing and Management capabilities, such as Early Packet
Discard, to comply with the latest standards of the ATM Forum. In addition, Vertical Flow
Control has been added to guarantee that vertically opposite SRE-Ls within a switch
fabric have no cell loss once a cell has been routed.
The SRE-L supports all of the features of the SRE with the addition of the following:
- Selectable per VC EFCI Marking
- Selectable per output queue Vertical Flow Control (VFC)
- Early Packet Discard (EPD) notification capability
- 25 MHz operation
- JTAG compliant
All inputs and outputs are 8-bit parallel, with independent strobe signals. The SRE selects
the relevant output for an incoming cell based on a routing tag previously appended to the
cell header. This function can be performed either by the Address Translation Controller or
the Adaptation Layer Controller, depending on the direction of data flow and the switch
configuration. Extensive simulation has been performed to analyse the behaviour of switch
fabrics based on the SRE for a wide variety of traffic types and loading factors.
As well as
regenerating the expansion output port signals to remove the need for any buffering
between switch elements, the pin-out of the SRE has been defined to enable devices to be
laid out on the board as shown. This enables extremely compact switches to be
constructed. One other interesting feature of the SRE is that the configuration parameters
are defined using the input expansion port pins of switches in the top row of the matrix. This
information is passed serially to all other SREs during system initialisation.
Since the number of elements in a matrix increases proportionally to the square of the
number of inputs, the SRE is best suited for relatively small switches (up to 32x32). This
should be adequate for most customer premises applications, however larger structures
can be achieved by connecting individual matrices in a multi-path delta configuration.
Each switch element can use a selectable part of the tag field, therefore intermediate
address translation/tag generation is unnecessary.
Package: ||PQFP 208 Pin|
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